Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally<1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens”; however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens”. Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). Another goal is to use as much of the semiconductor wafer real estate as possible. Even another goal is to optimize illumination and enhance the contrast of an image on a wafer. By increasing the overall process window (i.e., the ability to consistently print features having a specified CD regardless of whether or not the features are isolated or densely packed relative to adjacent features), one may be able to more easily accomplish each one of the goals.
Methods for optimizing the source illumination and mask patterns so as to improve the overall printing performance have been disclosed in the prior art. One such method is disclosed in U.S. Pat. No. 6,563,566 to Rosenbluth et al., incorporated herein by reference. Specifically, Rosenbluth discloses a lithographic optimization system that alleges to perform an optimization of source illumination and mask patterns to improve the printing of a given mask pattern. The function of merit utilized by Rosenbluth for determining the optimal combination of the source/mask pattern is the aerial image log-slope at a number of pre-selected points along the border of the pattern geometry. The optimization algorithm appears based on the assumption that the printing of a lithographic pattern is solely determined by the set of diffraction orders collected in the imaging pupil, independent of their location in the pupil plane.
While maximizing the aerial image log-slope at selected sampling locations in the pattern enhances the budget/tolerance for exposure variations, commonly referred to as the exposure latitude (EL), it does not help to increase the budget/tolerance for focus variations, commonly referred to as the depth of focus (DOF). Indeed, it is known that patterns that are optimized for EL under in-focus conditions (i.e., at zero DOF) show complementary results compared to patterns that have been optimized for typical process conditions that accommodate for defocus variations. Another problem is the occurrence of uneven line printing; that is, the contrast at a point on the middle of a line is greater than the contrast at a point at an end of a line formed in a resist. It is therefore desirable to optimize illumination to print features with greater precision, so as to enhance EL.
Polarization, though present in most illuminations, is negligible for low numerical aperture (NA) systems because angles of incident at the resist are shallow. Therefore, any negative or positive affects from polarization are minimal. As alluded to above, photolithographic imaging is moving towards smaller and smaller feature sizes, as would be expected. One of many ways to obtain smaller features is to increase the NA. However, angles of incidence at the resist increase, thus enhancing the negative affects caused by polarization and lessening image contrast. It is therefore desirable to overcome these problems, especially in higher NA systems.